Freescale Semiconductor /MKL28T7_CORE1 /LPUART1 /STAT

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Interpret as STAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)MA2F 0 (0)MA1F 0 (0)PF 0 (0)FE 0 (0)NF 0 (0)OR 0 (0)IDLE 0 (0)RDRF 0 (0)TC 0 (0)TDRE 0 (0)RAF 0 (0)LBKDE 0 (0)BRK13 0 (0)RWUID 0 (0)RXINV 0 (0)MSBF 0 (0)RXEDGIF 0 (0)LBKDIF

MA2F=0, LBKDIF=0, MA1F=0, NF=0, OR=0, LBKDE=0, MSBF=0, BRK13=0, RXINV=0, RAF=0, RWUID=0, PF=0, TC=0, RDRF=0, RXEDGIF=0, IDLE=0, FE=0, TDRE=0

Description

LPUART Status Register

Fields

MA2F

Match 2 Flag

0 (0): Received data is not equal to MA2

1 (1): Received data is equal to MA2

MA1F

Match 1 Flag

0 (0): Received data is not equal to MA1

1 (1): Received data is equal to MA1

PF

Parity Error Flag

0 (0): No parity error.

1 (1): Parity error.

FE

Framing Error Flag

0 (0): No framing error detected. This does not guarantee the framing is correct.

1 (1): Framing error.

NF

Noise Flag

0 (0): No noise detected.

1 (1): Noise detected in the received character in LPUART_DATA.

OR

Receiver Overrun Flag

0 (0): No overrun.

1 (1): Receive overrun (new LPUART data lost).

IDLE

Idle Line Flag

0 (0): No idle line detected.

1 (1): Idle line was detected.

RDRF

Receive Data Register Full Flag

0 (0): Receive data buffer empty.

1 (1): Receive data buffer full.

TC

Transmission Complete Flag

0 (0): Transmitter active (sending data, a preamble, or a break).

1 (1): Transmitter idle (transmission activity complete).

TDRE

Transmit Data Register Empty Flag

0 (0): Transmit data buffer full.

1 (1): Transmit data buffer empty.

RAF

Receiver Active Flag

0 (0): LPUART receiver idle waiting for a start bit.

1 (1): LPUART receiver active (LPUART_RX input not idle).

LBKDE

LIN Break Detection Enable

0 (0): Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).

1 (1): Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).

BRK13

Break Character Generation Length

0 (0): Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).

1 (1): Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).

RWUID

Receive Wake Up Idle Detect

0 (0): During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.

1 (1): During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.

RXINV

Receive Data Inversion

0 (0): Receive data not inverted.

1 (1): Receive data inverted.

MSBF

MSB First

0 (0): LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.

1 (1): MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].

RXEDGIF

LPUART_RX Pin Active Edge Interrupt Flag

0 (0): No active edge on the receive pin has occurred.

1 (1): An active edge on the receive pin has occurred.

LBKDIF

LIN Break Detect Interrupt Flag

0 (0): No LIN break character has been detected.

1 (1): LIN break character has been detected.

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